1. Field of the Invention
The present invention relates to a memory controller and a flash memory system. The present invention particularly relates to a memory controller and a flash memory system which control access to a flash memory having a multi-plane write function like a two-plane write function, etc.
2. Description of the Related Art
Recently, there is active development on a flash memory which is a non-volatile storage medium. The flash memory is becoming popular as a storage medium for information devices (host systems) such as a digital camera. The amount of data such an information device handles becomes huge. Accordingly, the memory capacity of the flash memory becomes larger.
It is necessary to smoothly manage the memory area of a large-capacity flash memory. For this purpose, there is a scheme of dividing the memory area of a large-capacity flash memory into a plurality of zones and managing the zones as disclosed in, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2005-18490.
Conventionally, the memory area of the flash memory having a plurality of zones is separated in the form shown in, for example, FIG. 7 for management.
A physical block includes a predetermined number of pages which are the physical units of data reading and writing. The physical block is a unit of data erasure. A unique Physical Block Address (PBA) is assigned to each physical block. Each physical block is classified into one of a plurality of physical zones. A unique Physical Zone Number (PZN) is assigned to each physical zone. For example, FIG. 7 shows 2048 physical blocks. Sequential PBAs, #0 to #2047, are assigned to the physical blocks. A total of 512 physical blocks with PBAs #0 to #511 belong to a physical zone with PZN #0. A total of 512 physical blocks with PBAs #512 to #1023 belong to a physical zone with PZN #1. A total of 512 physical blocks with PBAs #1024 to #1535 belong to a physical zone with PZN #2. A total of 512 physical blocks with PBAs #1536 to #2047 belong to a physical zone with PZN #3.
The host system manages the address space by a Logical Block Address (LBA). An LBA is a sequential number given to each area when the address space is separated into sector areas (each sector consisting of 512 bytes). A group of sector areas is called “logical block”. A group of logical blocks is called “logical zone”. A sequential number given to a logical block is called “Logical Block Number (LBN)”. A sequential number given to a logical zone is called “Logical Zone Number (LZN)”. A sequential number given to a logical block included in each logical zone is called “Logical Zone Internal Block Number (LZIBN)” in the logical zone.
Given that the number of logical blocks included in each logical zone is n, the quotient of dividing LBN by n corresponds to LZN, and the remainder corresponds to LZIBN.
One physical zone is assigned to each logical zone. Data corresponding to each logical block included in a logical zone is written in a physical block included in the physical zone that is assigned to the logical zone. A physical block has a redundant area in which information indicating the logical block corresponding to the written data in the physical block is written. Hereinafter, this information is called “logical address information”.
In each physical block, data in the logical blocks allocated to that physical block are written in the order of LBAs. Therefore, the correlation between the LBA given from the host system and an access area in the flash memory can be managed by managing the correlation between physical blocks and logical blocks.
The correlation between physical blocks and logical blocks changes every time data writing or data erasure is executed. This makes it necessary to manage the correlation between both physical and logical blocks at each point of time. An address translation table is created to effect such management. The address translation table is updated every time the correlation between physical blocks and logical blocks changes. The correlation between logical zones and physical zones is preset. Therefore, the address translation table for each logical zone can be created by referring to the logical address information written in the redundant area in a physical block included in each physical zone.
LBN as well as LZIBN is used as logical address information. In general, LZIBN is written in the redundant area as logical address information because LZIBN has a smaller amount of data than LBN does.
The number of sector areas included in each logical block is set according to the number of sectors included in that physical block which is correlated with the logical block. Suppose that a flash memory in use is configured so that one physical block consists of 32 pages each corresponding to one sector area. In this case, if one logical block corresponds to one physical block, 32 sector areas are included in one logical block.
In the example of FIG. 7, the number of sector areas included in one logical block is 32. 16,000 sector areas with LBAs #0 to #15999 are allocated to the logical zone with LZN #0. 16,000 sector areas with LBAs #16000 to #31999 are allocated to the logical zone with LZN #1. 16,000 sector areas with LBAs #32000 to #47999 are allocated to the logical zone with LZN #2. 16,000 sector areas with LBAs #48000 to #63999 are allocated to the logical zone with LZN #3.
In the example of logical zones shown in FIG. 7, 16,000 sector areas are allocated to each logical zone. In each logical zone area, areas each consisting of 32 sectors are managed as logical blocks. The LBAs of the 32 sector areas belonging to each logical block are sequential. In other words, 32 sector areas with consecutive LBAs are one logical block. 500 (LZIBNs #0-#499) logical blocks with consecutive LBNs are allocated to each logical zone. The above configuration is just an example. The number of sector areas included in one logical blocks may be adequately set in such a way that the number of sector areas included in one logical block matches with the memory capacity of a plurality of physical blocks. Data is stored in the sequential order of LBAs in each page of a physical block. Therefore, an access destination in the flash memory is specified based on the correlation between logical blocks included in each logical zone and physical blocks included in that physical zone which is associated with the logical zone.
There is a two-plane flash memory having two planes as prior art. The prior art is described, for example, in Samsung's manual (Samsung Electronics, “K9XXG08UXM”, [online], URL: http://www.samsung.com/Products/Semiconductor/NANDFlash/SLC_LargeBlock/16G bit/K9WAG08U1M/ds_k9xxg08uxm_rev10.pdf, retrieved from internet on 2006 Apr. 15.). This plane includes a memory cell array having a plurality of memory cells, and a register for accessing the memory cell array. In this two-plane flash memory, like an ordinary one-plane flash memory, the memory cell array is separated into physical blocks which are erasure units. Each physical block is separated into pages which are write or read units.
FIG. 8 shows an example of the two-plane flash memory. The two-plane flash memory includes a plane #0 and a plane #1. PBAs are alternately assigned to the physical blocks of the plane #0 and the plane #1. For example, the plane #0 has 2,048 physical blocks with PBAs #0, #2, #4 up to #4094. The plane #1 has 2,048 physical blocks with PBAs #1, #3, #5 up to #4095.
Each physical block in the two-plane flash memory includes 64 pages as shown in FIG. 9A. 64 page numbers #0 to #63 are assigned to each page.
As shown in FIG. 9B, each page includes a data area (“main field” in the flash memory disclosed in the aforementioned Samsung's manual) and a redundant area (“spare field” in the flash memory disclosed in the Samsung's manual). The data area stores data given from the host system. The data area has 4 sectors (512 bytes×4=2048 bytes). The redundant area is a 64-byte area for storing additional information. Additional information includes for example an Error Correcting Code corresponding to data in the data area.
A register #0 and a register #1 as shown in FIG. 8 are memory areas for temporarily holding data. The “data” here is data to be written in the data area (2048 bytes) and the redundant area (64 bytes) of each page, or data read from the data area (2048 bytes) and the redundant area (64 bytes).
In the two-plane flash memory, data held in the register #0 and register #1 shown in FIG. 8 can be written in the flash memory in a write system called two-plane write. In the two-plane write, data is written in pages of a preset pair of physical blocks (a physical block in the plane #0 and a physical block in the plane #1). In other words, these two physical blocks are associated with each other.
When one logical block is allocated to one pair of physical blocks, 512 sector areas (sector numbers #0-#511) included in the logical block are allocated in the pages of the pair of physical blocks in the order shown in FIG. 10. That is, the area with sector numbers #0-#3 are allocated to the page number #0 in the plane #0, sector numbers #4-#7 are allocated to the page number #0 in the plane #1, sector numbers #8-#11 are allocated to the page number #1 in the plane #0, sector numbers #12-#15 are allocated to the page number #1 in the plane #1, and so forth. Sector numbers #504-#507 are allocated to the page number #63 in the plane #0, and sector numbers #508-#511 are allocated to the page number #63 in the plane #1.
A plane-by-plane write timing chart and a timing chart for two-plane write (two-plane page program in the flash memory disclosed in the aforementioned Samsung's manual) will be described below. The normal writing is carried out as shown in a timing chart in FIG. 11A. An input command “IC” instructing data writing to the register, a write destination address “AD” and write data “DT”, and a write command “PC” instructing writing to the memory cell array from the register are supplied to the plane #0 or the plane #1 in the flash memory in order. In the flash memory disclosed in the Samsung's manual, a busy time of 200 μsec occurs after the supply of the write command “PC”. The data written in the register is written in the memory cell array during the busy time.
The timing chart for two-plane write is shown in FIG. 11B. First, an input command “IC”, a write destination address “AD” and write data “DT”, and a dummy write command “DPC” are supplied to the plane #0. Then, a dummy input command “DIC”, the write destination address “AD” and write data “DT”, and a write command “PC” are supplied to the plane #1. In the two-plane write, a dummy busy time of 0.5 μsec occurs after the supply of the dummy write command “DPC”. The data written in the register of the plane #0 and the register of the plane #1 are simultaneously written in the flash memory after the write command “PC” is supplied thereto. The busy time that occurs at the time of the writing is 200 μsec which is the same as the busy time which occurs at the time of data writing to one plane, either the plane #0 or the plane #1. That is, in two-plane write, the amount of data to be written in the flash memory is equivalent to the amount of data in two registers. However, the busy time that occurs in the writing process is approximately the same (0.5 μ+200 μ=200.5 μ) as the busy time (200 μsec) that occurs in the normal writing, i.e., in data writing in one register. The two-plane write therefore achieves fast data writing.
However, the two-plane write is executed with respect only to an associated free physical blocks i.e. a preset pair of physical blocks. When one of the pair of physical blocks becomes a defective block, therefore, only normal writing is performed to the other physical block. When fast writing is desired, therefore, it is necessary to use a pair of physical blocks to which two-plane write is enabled by priority. There may be a case where the number of pairs of physical blocks each having good (non-defected) blocks becomes smaller so that no further pairs of physical blocks to which two-plane write is enabled can be secured as far as the preset condition is concerned. In this case, a memory area cannot be secured unless a good block in a pair of physical blocks one of which has become a defective block is used.